This application is based upon and claims priority from prior French Patent Application No. 00-10176, filed Aug. 2, 2000, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The present invention relates to semiconductor device fabrication, and more specifically to a process for fabricating a substrate having a xe2x80x9csilicon-on-insulatorxe2x80x9d or xe2x80x9csilicon-on-nothingxe2x80x9d architecture.
2. Description of Related Art
A xe2x80x9csilicon-on-insulatorxe2x80x9d (SOI) or xe2x80x9csilicon-on-nothingxe2x80x9d (SON) architecture with thin silicon films and, where appropriate, a buried dielectric is particularly desirable for its properties with respect to control of short channel effects. These properties mainly result from the fact that the very thin silicon film in which the semiconductor device is produced helps control the gate on the channel, while handicapping control via the source and drain. With regard to the very thin buried dielectric film, this handicaps electrostatic coupling between the source and drain through the buried dielectric.
Currently, commercially-available SOI substrates are incapable of providing sufficiently small silicon film thicknesses and buried dielectric thicknesses to allow effective control of the gate over the channel, and therefore of the short channel effects. In particular, film thicknesses of at most 20 nm in the case of the silicon and at most 30 nm in the case of the dielectric would be necessary. The current silicon film thicknesses are at least 50 nm and those of the buried dielectric are at least 80 nm. In both cases, it must be assumed that there is a scatter of xc2x110 nm. Such a scatter prevents the obtaining of a nanometric silicon film by localized thinning of the SOI substrate (for example, through a LOCOS process).
Certain techniques can be used to reduce the thickness of the silicon layer, such as the xe2x80x9cwafer bondingxe2x80x9d and xe2x80x9csmart-cutxe2x80x9d techniques. However, both of these techniques rely on the use of two wafers of initial substrate and expensive processes involving implantation, oxidation, chemical-mechanical polishing, almost complete abrasion of the substrate, etc.
In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to provide a simple and inexpensive process for fabricating a SOI or SON substrate on which a semiconductor device can be produced.
Another object of the present invention is to provide a process for fabricating a SOI or SON substrate from a single bulk silicon substrate, without the use of chemical-mechanical polishing or substrate abrasion.
Yet another object of the present invention is to provide a process for fabricating a SOI or SON substrate that allows extremely thin silicon and buried dielectric layers to be obtained.
A further object of the present invention is to provide a substrate having at least one active region of SOI or SON architecture surrounded by insulating regions.
One embodiment of the present invention provides a method for fabricating a substrate of SOI architecture. According to the method, a multilayer stack is grown by non-selective full-wafer epitaxy on an initial substrate, with the multilayer stack including a Ge or SiGe alloy first layer and a silicon layer on the first layer. Active regions are defined and masked, and insulating pads are formed so as to be located on the perimeter of each of the active regions at predetermined intervals and placed against sidewalls of the active regions. Trenches are etched for separating the active regions, and the Ge or SiGe alloy first layer is laterally etched so as to form an empty tunnel under the silicon layer. The tunnel is filled with a dielectric material, and the trenches are filled with a dielectric material. In a preferred embodiment, the Ge or SiGe alloy first layer has a thickness of between about 1 and 50 nm, and the silicon layer has a thickness of between about 1 and 50 nm.
Another embodiment of the present invention provides a method for fabricating a substrate of SON architecture. According to the method, a multilayer stack is grown by non-selective full-wafer epitaxy on an initial substrate, with the multilayer stack including a Ge or SiGe alloy first layer and a silicon layer on the first layer. Active regions are defined and masked, and insulating pads are formed so as to be located on the perimeter of each of the active regions at predetermined intervals and placed against sidewalls of the active regions. Trenches are etched for separating the active regions, and the Ge or SiGe alloy first layer is laterally etched so as to form an empty tunnel under the silicon layer. The trenches are filled with a dielectric material. In a preferred embodiment, the Ge or SiGe alloy first layer has a thickness of between about 10 and 30 nm, and the silicon layer has a thickness of between about 5 and 20 nm.
Further embodiments of the present invention provide substrates that include at least one active region of SOI or SON architecture, insulating trench regions surrounding the active region, and insulating pads located in the insulating trench regions around the perimeter of the active region, and placed against sidewalls of the active region.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.